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Arm Machine-Learning Core Scales Up

May 28, 2019

Author: Mike Demler

At Computex, Arm announced general availability of production RTL for its first neural-network accelerator, although it has yet to baptize the design with a brand name such as Cortex or Mali. The accelerator officially carries the generic label “machine-learning processor” (MLP). In 2Q18, the company disclosed preliminary details of the new core, but the production version increases power efficiency and performance, and it includes a multicore option that allows connection of eight cores to deliver up to 32 trillion operations per second (TOPS).

The MLP connects to a host CPU through its Ace-Lite interface, and each MLP core can integrate up to 16 parallel compute engines (CEs). The CEs share an embedded microcontroller that distributes the workload. They share DMA and sync units as well. The data-flow architecture comprises a feature-map reader, a weight decoder, a convolution engine, a programmable-layer engine, and one 64KB SRAM per CE to store weights and activations. The decoder processes weights in a compressed format. The CEs also compress activations before storing them in the local SRAM, reducing bandwidth requirements by up to 3x relative to uncompressed data.

The convolution engine integrates 128 INT8 multiply-accumulate (MAC) units, which also support INT16 operations. For INT8 precision, the maximum performance per core is 4 TOPS. The company originally positioned the MLP for mobile devices, where 4 TOPS is more than sufficient. But Apple, MediaTek, Qualcomm, and Samsung have designed their own DLAs, and some reports indicate Huawei has, too. That market will be difficult for the MLP to break into. Because of the limited mobile-processor opportunities, we expect the company added multicore support to address automotive, video surveillance, and other high-performance applications.

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