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Achronix Debuts FPGAs for AI

June 4, 2019

Author: Tom R. Halfhill

As promised last year, Achronix is using its embedded-FPGA technology to build a new FPGA family optimized for machine learning and data throughput. To compete with Intel and Xilinx FPGAs in data centers, the new Speedster7t family employs faster DSP blocks, optional GDDR6 memory, 400 Gigabit Ethernet, PCI Express Gen5, 7nm FinFETs, and a custom on-chip network. Relative to competing products, its DSPs are more optimized for machine learning (ML) and its I/O interfaces are more geared to high bandwidth. One tradeoff, however, is that it lacks the Arm CPUs that other advanced FPGAs integrate for general embedded applications.

Differentiation is vital if Achronix is to avoid the chronic crashes that have thwarted other attempts to challenge the FPGA duopoly of Xilinx and Intel (Altera). One approach is to lay a custom interconnect over the conventional FPGA fabric, which is bounded by interfaces for high-speed networking and external memory. The on-chip network resembles a mesh but is actually a grid of Amba AXI buses. It’s simpler than a true mesh and provides faster pathways between the chip’s I/O interfaces and processing elements than the usual method of routing data through the configurable fabric.

To bring ASIC-like processing to this design, Achronix has also built new DSP blocks optimized for low-precision multiplication. Called machine-learning processors (MLPs), these hard-logic blocks are twice as powerful as those introduced last year in its SpeedCore7t embedded-FPGA intellectual property (eFPGA IP). With additional help from the fabric’s multipliers, the top-end Speedster7t 6000 FPGA can execute up to 134 trillion operations per second (TOPS) on 8-bit-integer (INT8) data. Achronix says the initial Speedster7t design will tape out in June and sample in 4Q19.

Subscribers can view the full article in the Microprocessor Report.

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