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An Inside Look at AI Accelerators

August 6, 2019

Author: Linley Gwennap

Most smartphone-processor vendors have been somewhat closemouthed about their deep-learning accelerators (DLAs), hoping to gain an advantage over competitors. Once their chips reach production, however, their design decisions become more apparent. Our analysis of recent die photos reveals rapid innovation as these vendors deploy their second- and third-generation designs. Apple, for example, moved from a dual-core DSP in the A11 to a DLA using eight custom cores in the A12. Optimized for neural networks, these cores are smaller but twice as powerful as the older DSPs.

MediaTek and Qualcomm had also used dual DSP cores in previous generations but more recently extended their designs, adding in-house accelerators that include large arrays of multiply-accumulate (MAC) units. These arrays efficiently handle the MAC calculations that are common in convolutional neural networks (CNNs). Most of the popular AI-enabled mobile applications (such as face unlock) employ CNNs for vision and image processing. The MAC accelerators implement 8-bit integer (INT8) calculations, which consume less power than 16- or 32-bit floating-point (FP16 or FP32) operations. But neural networks developed in FP32 must be “quantized” before they can run in INT8 mode.

Our die-photo analysis shows that the latest premium processors from Apple and Samsung devote about 5% of their die area to DLAs, whereas the Snapdragon 855 DLA requires nearly 8%. (We thank our friends at TechInsights for providing high-quality die photos for this analysis.) MediaTek’s Helio P90 targets “mid-premium” smartphones that cost less than premium models, so the company had to adopt a lower transistor budget for its DLA. Even so, the P90 delivers premium performance on mobile tests such as AI-Benchmark and Master Lu’s AI benchmark. Measuring AI performance remains a challenge, however, and these two tests yield somewhat different results.

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