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Broadcom Ships PCIe Gen4 Switches

September 24, 2019

Author: Bob Wheeler

August marked a turning point for PCI Express 4.0, better known as PCIe Gen4. The PCI-SIG completed its first Gen4 compliance tests, and its integrator’s list includes a processor (root complex), a handful of controller (end point) chips, and one switch chip. The lattermost device is Broadcom’s PEX88000, which sampled last year and is now in production. The lone processor on this list—AMD’s Epyc 2 (Rome)—is a critical ecosystem component; OEMs will ship the first Rome-based servers this month.

The PEX88000 family comprises PCIe 4.0 switch chips with 24 to 96 lanes and the same number of ports. They handle port widths from 1 to 16 lanes, and each port can operate at a different rate (e.g., Gen3 or Gen4). Broadcom claims cut-through latency of 105ns between a pair of x16 ports, representing a 30% reduction from the PEX9700 Gen3 family. The PEX88000 adds an Arm Cortex-R4 CPU, eliminating the need for an external management processor. The family spans a range of options: the 96-lane PEX88096 comes in a 37.5mm by 42.5mm package and dissipates 36W (typical), whereas the 24-lane PEX88024 fits in a 27mm by 24mm package and dissipates 11W.

With servers shipping and PCI-SIG compliance testing available, PCIe Gen4 is poised for 2020 deployment. We expect Intel’s Cooper Lake server processor, due to ship in 1Q20, will be the first Xeon to handle Gen4. By designing the PEX88000 into storage systems, customers can immediately benefit from AMD and Intel Gen4 hosts while still employing Gen3 SSDs, upgrading to Gen4 SSDs when they become available.

Subscribers can view the full article in the Microprocessor Report.

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