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Ceva and Synopsys Spin More TOPS

October 8, 2019

Author: Mike Demler

The rapid adoption of machine learning is driving IP vendors to compete by scaling up performance in each new generation of licensable deep-learning accelerators (DLAs). Last year, DLAs integrating up to 4,096 multiply-accumulate (MAC) units per core set the standard for licensable inference engines. But advanced driver assistance systems (ADASs) and other high-performance edge devices demand even greater performance, so with their latest products, Ceva and Synopsys aim to shatter that mark.

Ceva recently announced its second-generation NeuPro-S. The company didn’t change the core NeuPro engine architecture, which can run all common neural-network layers, but it added a new multilevel memory subsystem (MSS) that allows multiple cores to work together sharing the same on-chip memory. An engine integrating 4,096 MAC units delivers up to 12.7 trillion operations per second (TOPS). NeuPro-S customers typically aggregate up to eight engines comprising a total of 32K MAC units, delivering up to 100 TOPS, but there is no hard limit.

Synopsys has enhanced its DesignWare ARC EV6x DLAs, which allow customers to connect multiple accelerator arrays, each integrating 880 MAC units along with dedicated blocks for activations and fully-connected layers. The EV6x models support up to four arrays comprising 3,520 MAC units, but the new EV7x quadruples that to 16 arrays comprising a total of 14,080 MAC units. Along with supporting more MAC units, the EV7x improves the engine’s accuracy, bandwidth, and MAC utilization. At 1.25GHz, the EV7x delivers up to 35 TOPS. To match Ceva’s multicore capabilities, customers can connect multiple EV7x instances with shared cluster memory using an AXI bus or a network-on-chip (NoC).

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