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SiFive U8 Takes RISC-V Out of Order

October 29, 2019

Author: Bob Wheeler

Continuing its annual cadence, SiFive disclosed its highest-performance RISC-V core to date at the Linley Fall Processor Conference. The U8-series builds on the 64-bit superscalar U7-series by adding out-of-order (OOO) execution, a first for commercial RISC-V intellectual property (IP). The first core in the new series is the low-power U84, which includes a double-precision floating-point unit (FPU) and offers the same multicore configurations and Linux compatibility as the U74. In mid-2020, SiFive plans to release the U87, its first CPU to sport a vector unit.

The company designed the U84 to target the same performance as Arm’s Cortex-A72, but the latter CPU is about five years old. It overdesigned portions of the U8 architecture, however, to support higher-performance variants that will follow the U84. For example, the U8 front end can decode up to four instructions per cycle (IPC), but the U84 instantiates only three decoders. The U84’s 12-stage pipeline achieves an estimated 2.3GHz in a fully synthesized 16nm design and typical process corner. Like the U74, the U84 omits private L2 cache, relying instead on an L2 shared by all cores.

The U84 slots in between Arm’s newest little and big Cortex CPUs in per-clock performance. Customers who want the best single-thread performance in the newest process node can select Cortex-A77. If they need better area efficiency, however, the U84 delivers an attractive compromise.

Subscribers can view the full article in the Microprocessor Report.

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