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Mythic Reveals Data-Flow Architecture

November 5, 2019

Author: Bob Wheeler

As AI startup Mythic prepares to sample its first products, it’s revealing more digital-architecture details. Its deep-learning accelerator (DLA), which it calls an intelligence processing unit (IPU), handles inference tasks—mainly convolutional neural networks (CNNs). The chip uses NOR flash memory to perform matrix multiplication in the analog domain, but conventional digital circuits distribute input data, collect results, handle nonconvolutional layers, and manage data flow. At the recent Linley Fall Processor Conference, Mythic CTO Dave Fick revealed the chip’s data-flow architecture. It includes an element the company calls a flow scoreboard that holds control state for each matrix-multiply-accelerator (MMA) core.

Mythic is testing first silicon in its lab and expects to deliver samples to customers next quarter, with production scheduled for later next year. It initially plans to offer three accelerator cards: an M.2 x4 module with a single DLA, a PCIe x4 card with four DLAs, and a PCIe x16 card with 16 DLAs. The multiple-DLA cards include a PCIe switch that enables peer-to-peer communication in addition to multiplexing the host interface. The company targets edge applications where it believes its analog approach will yield a performance-per-watt advantage.

In the meantime, the AI-inference landscape continues to evolve as new products reach the market. Mythic’s closest DLA competitor may be Intel’s new Nervana NNP-I 1000 (Spring Hill). Mythic employs a 40nm embedded-flash process at UMC, whereas Spring Hill requires a sizable die in Intel’s leading-edge 10nm process. Although Mythic withheld die size, its DLA should cost less to manufacture.

Subscribers can view the full article in the Microprocessor Report.

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