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ARC VPX5 Sports Four-Way VLIW

November 12, 2019

Author: Mike Demler

The new VPX5 is the first Synopsys ARC DSP to employ a VLIW architecture. Although the company’s ARC EM and HS controllers provide DSP extensions, the VPX5 is a true DSP that increases performance by executing load/store and other scalar operations in parallel with vector/SIMD operations. An optional vector floating-point engine delivers a big performance boost by integrating four vector floating-point units (VFPUs). To satisfy automotive functional-safety requirements, the company plans to offer a VPX5FS model with additional ASIL B/D features, including lockstep operation.

In the VXP5’s vector floating-point engine, three of the VFPUs handle general-purpose ALU and multiply-accumulate (MAC) operations on half-, single, and double-precision data. A fourth unit includes accelerators for floating-point math operations commonly used in linear algebra, such as exponential, log, and trigonometric functions.

The VPX5 core contains a scalar CPU and multiple vector units that support 8-, 16-, and 32-bit integer SIMD computations in a 512-bit vector. The CPU implements the ARC HS pipeline, but Synopsys updated it for tight integration in the VPX5. It works with L1 instruction and data caches of undisclosed configurations and sizes. The vector units each have three ALUs, a hardware multiplier, and a MAC unit.

The company supports the VPX5 with the nSim ISA simulator, which lets designers develop software before receiving working silicon. Along with an ISO 26262 software package and safety documentation, the VPX5 provides functional-safety features, math engines, and floating-point performance that’s well suited to the automotive systems it targets.

Subscribers can view the full article in the Microprocessor Report.

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