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TI Jacinto Accelerates Level 3 ADAS

March 3, 2020

Author: Mike Demler

The TDA4VM is the offspring of Texas Instruments’ C6x Keystone DSPs and OMAP 5 application processors. It joins the DRA829V gateway processor as the first products in the company’s new Jacinto 7-series. For the previous Jacinto 6 line, TI adapted the Keystone and OMAP technologies to create automotive-infotainment processors that support basic (Level 1) ADAS functions, such as traffic-sign recognition. The new chip, however, provides a big performance boost that enables it to power Level 2/3 systems. The TDA4VM retains infotainment features, but it also sports a new DSP-based deep-learning accelerator (DLA) that delivers eight trillion operations per second (TOPS).

Like the DRA829V, the TDA4VM integrates four subsystems operating in three isolated domains. The two processors have identical safety-island and wakeup subsystems, which employ Cortex-R5F and Cortex-M3 CPUs, respectively. The primary domain integrates the same Cortex-A72 and Cortex-R5F CPUs, but it adds a new C7x DSP with a wider vector/SIMD engine than the C6x, along with a tightly coupled accelerator that integrates 4,096 MAC units. It also has two updated C6x DSPs, a PowerVR GPU, a video codec, and a video-capture subsystem that supports eight surround-view cameras.

The Jacinto 7 chips are manufactured in 16nm technology. The TDA4VM integrates about 3.5 billion transistors, including a total of 25MB in multiple SRAMs. TI is shipping preproduction samples for both products now: each sells for $97 in 1,000-unit quantities. The company plans to begin volume production in 2H20. It also offers a $400 TDA4VMx evaluation module (EVM) that works with a $1,500 common-processor board. Other plug-in cards are available, too, and TI works with several partners to supply a variety of ADAS software tools.

Subscribers can view the full article in the Microprocessor Report.

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