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First 112Gbps PAM4 PHYs Arrive

April 7, 2020

Author: Bob Wheeler

After playing catch-up in first-generation PAM4 technology, Marvell is now among the leaders as 112Gbps PAM4 electrical interfaces come to market. Last month, it announced sampling of the industry’s first system-side Ethernet PHY to handle 112Gbps lanes, allowing 100Gbps-per-wavelength optical modules to omit 2:1 multiplexing (gearboxing). At the same time, Inphi announced the industry’s first optical-module PHY with 112Gbps electrical interfaces. With 400Gbps Ethernet optics now shipping to hyperscale-data-center operators, chip vendors are preparing the transition from 8x56Gbps to 4x112Gbps chip-to-module (C2M) interfaces.

Marvell’s new 88X9121P is an 800Gbps bidirectional PHY that handles 2x400GbE, 4x200GbE, or 8x100GbE ports. It’s fully symmetric, meaning there isn’t a system side and a line side: both sides implement the same serdes. For 112Gbps interfaces, both sides have eight transceivers the company rates as medium reach (MR). The 112Gbps transceivers also support 56Gbps PAM4 and 28Gbps NRZ, whereas eight additional transceivers on each side support only 56/28Gbps (and lower) rates. Thus, the chip handles 16x56Gbps as well as 8x112Gbps interfaces, enabling it to gearbox at its maximum 800Gbps full-duplex bandwidth.

Also sampling, Inphi’s new Spica is the industry’s first 800Gbps PAM4 PHY for optical modules. It doubles the bandwidth of the company’s shipping Porrima PHY by adopting 112Gbps PAM4 lanes for the module connector and doubling the width of the optoelectronic I/Os. For the transmitter, Spica integrates drivers for directly modulated lasers. For the receiver, it connects to Inphi’s IN5665TA 8x56Gbaud linear transimpedance amplifier (TIA). Its C2M electrical interface includes 8x112Gbps serdes designed to meet the draft 802.3ck AUI specification. By using 7nm technology, Inphi enabled its DSP-based design to serve 800Gbps optical modules consuming 14W.

Subscribers can view the full article in the Microprocessor Report.

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