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Synopsys Launches 64-Bit ARC

April 14, 2020

Author: Mike Demler

Synopsys has developed its first 64-bit ARC CPU cores, called the HS6x family, implementing its new ARCv3 ISA. ARCv3-based cores are software compatible with previous-generation ARC cores, but they add instructions that the new 32-bit HS5x family supports as well. The HS6x and HS5x target solid-state drives (SSDs), networking equipment, wireless infrastructure, and other high-performance embedded systems. Production RTL is scheduled for general licensing in 3Q20.

Previous-generation ARC CPUs can serve in dual- and quad-core cache-coherent clusters. But in response to customer demand for higher-performance embedded processors, the company developed a new interconnect that raises the limit to 12 cores—more than any other licensable CPU. The new high-speed interconnect can deliver up to 800GB/s of intracluster bandwidth, and according to the company’s calculations, it reduces by 80% the number of wires between cores and the rest of the cluster, increasing area efficiency. 

All of the new HS cores support the optional FastMath pack, which plugs into the instruction space reserved for the ARC Processor Extension (Apex). FastMath increases performance for a subset of math operations that DSPs often employ, such as exponential, logarithm, square root, and trig functions. Designers can also include a trace block that works with CoreSight and Nexus debug, as well as a cluster DMA, FPU, and MPU. The scalar FPU operates with a dedicated register file. Half-precision (FP16) support is a new feature; along with single-precision (FP32), the HS6x handles double precision (FP64) as well.

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