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RISC-V Vectors Know No Limits

April 28, 2020

Author: Tom R. Halfhill

At least five years in the making, RISC-V vector extensions are finally nearing approval. They impose almost no limits on the size or number of data elements, and they allow mixed-width elements to execute in the same instruction stream with fixed-width elements and general-purpose instructions. They can operate on all data types, and compiled binaries will run on any implementation. CPU designs now under way range from microcontroller-class cores with 32-bit vectors to supercomputer-class cores with 16,384-bit vectors.

The 32-bit RISC-V Vector (RVV) specification will soon advance from v0.8 to v0.9. (The same instruction set will work with future 64- and 128-bit encodings.) The V-extension task group expects to propose the v1.0 specification by the end of June, kicking off a 45-day review for final comments. Assuming no serious objections, the community board could adopt the spec in August. RISC-V vendors can then begin shipping production RTL for CPUs with the extensions. SiFive already has three cores in development.

RVV extensions depart from the single-instruction, multiple-data (SIMD) extensions for proprietary CPUs, which fix in hardware the vector widths and numbers of elements (lanes). As the need for more parallelism has grown, SIMD extensions have expanded to 512 bits or more. Each iteration adds dozens or hundreds of new instructions, and newer code usually won’t run on older implementations.

By contrast, RVV extensions can adapt to different microarchitectures at run time. They target diverse CPU designs while maintaining binary compatibility, although code compiled for a specific implementation will run faster. Programmers can write code in assembly language or in a high-level language by using intrinsic functions or a vectorizing compiler. The main competitors are Intel’s AVX-512 and Arm’s Scalable Vector Extension (SVE), but both are more conventional than RVV.

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