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Andes Plots RISC-V Vector Heading

May 26, 2020

Author: Mike Demler

RISC-V International, formerly the RISC-V Foundation, expects to release its v1.0 vector-extension (RVV) specifications in August. But Andes has already delivered the first CPU core to support the new features. The NX27V is a 64-bit design that implements the RISC-V RV64 ISA, RVV, and proprietary Andes extensions. The scalar processing unit employs the same architecture as the company’s NX25: a single-issue five-stage microcontroller CPU. The new vector processing unit (VPU) adds configuration options for 128-, 256-, and 512-bit SIMD operations. Andes recently delivered production RTL to its lead customer, which is using it in a 7nm design. The NX27V should be available for general licensing in October.

Andes customers are evaluating the NX27V for digital basebands, image/vision processing, and neural-network acceleration. In those cases, the company expects designers will employ multiple NX27Vs along with a small RISC-V or Arm Cortex-A CPU that handles control operations. The new core also supports FFTs and other data-intensive DSP functions.

The NX27V will be attractive to customers that need more vector-processing performance than Arm’s Cortex-M55 provides, but designers should evaluate the power, performance, and area (PPA) tradeoffs. A dedicated DLA is better for neural-network inference, typically offering a more streamlined data-flow architecture with larger arrays of multiply-accumulate (MAC) units. Yet the Andes core is a capable acceleration coprocessor that can boost audio/video compression, handle networking memcpy operations, and perform other array-processing tasks. By delivering a product ahead of the final RVV ratification, the company has established more than a six-month lead over its rivals.  

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