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Lakefield Shrinks x86 SoCs

June 30, 2020

Author: Tom R. Halfhill

Intel’s Core Hybrid processors (code-named Lake­field) are the first to employ the company’s Foveros die-stacking technology. They bond a 10nm CPU die to a new 22nm south-bridge chip, then use conventional package-on-package (PoP) technology to add 4GB or 8GB of DRAM. Everything squeezes into an impressively compact 12mm x 12mm x 1mm package.

They’re also the first Intel processors with a “hybrid” cluster of large and small CPUs. In all, they have five CPU cores, an integrated GPU, an image processor, a video accelerator, an audio DSP, a PCI Express controller, and other I/O interfaces. Smaller than a dime, these SoCs are moving the x86 architecture into slimmer notebooks and tablets than ever before. They also counter Arm-based chips aspiring to Intel’s mobile-PC success.

Intel disclosed some high-level information about Lakefield last year when announcing Tremont, the newest x86 microarchitecture in the low-power Atom family. The latest announcement reveals more details, introducing two models: the Core i3-L13G4 and Core i5-L16G7. As is common for Intel, they employ the same silicon, but the i3 model operates at lower clock frequencies and disables part of the GPU.

Lakefield follows Arm’s Big.Little strategy of combining large CPUs that excel in single-thread performance with smaller CPUs that assume lighter workloads. In this case, it has one large Sunny Cove core and four small Tremont cores. This configuration increases power efficiency versus the usual homogeneous design and reduces leakage when the large core sleeps. Also, lower power allows the system to run on a smaller battery. Consequently, Lakefield enables Intel customers to design slimmer notebooks and tablets that deliver more performance than was possible using previous x86 chips.

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