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Stratix 10 NX Adds AI Blocks

July 14, 2020

Author: Linley Gwennap

Intel is determined to cover all aspects of the AI-accelerator market. Its latest offering for neural networks is the Stratix 10 NX, a new family in its 14nm FPGA line that revamps the DSP block to improve AI performance. In particular, the new design, which Intel calls the AI tensor block, is optimized for the 8-bit integer (INT8) data typically used in neural-network inferencing rather than the 18-bit data often used for digital signal processing. This change helped the company pack in 15 times more multipliers, greatly increasing multiply-accumulate (MAC) throughput. The first Stratix 10 NX products are now sampling, with production scheduled for the fourth quarter.

The company withheld details of the Stratix 10 NX models but said they’ll be similar to the current Stratix 10 MX products in logic density and other features. These high-end FPGAs range from 1.68 million logic elements (LEs) in the MX1650 to 2.08 million in the MX2100. The latter has 3,960 DSP blocks and carries a peak-performance rating of 16 trillion integer operations per second (TOPS) at 1.0GHz. It supports high-speed I/O including 100G Ethernet using 58Gbps serdes. All MX models are copackaged with High Bandwidth Memory (HBM2).

Intel has already announced its initial 10nm FPGA products, the Agilex F- and I-series, which it says will enter production “soon.” (The larger Agilex M-series has been delayed.) The Agilex DSP block natively handles Bfloat16 and INT8 data; the largest announced Agilex product has 2.7 million LEs and is rated at 51 TOPS. The company also offers its Habana Gaudi accelerator, a dedicated AI-inference design that we estimate at more than 100 TOPS. We expect the new Stratix parts to achieve up to 128 TOPS for customers that want to design their own accelerator.

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