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Ice Lake-SP Boosts Memory and I/O

September 8, 2020

Author: Bob Wheeler

Poor old Purley is three years old, and it can’t keep up with younger rivals. Due at year-end, Intel’s Whitley platform will deliver badly needed updates including more memory channels and PCI Express Gen4. Because Intel redesigned Cooper Lake just for scale-up servers, the platform will host only a single Xeon generation: Ice Lake-SP. The company used Hot Chips to disclose details of that chip, which brings its 10nm process to servers for the first time. Unfortunately, it’s the 2019 version, not the faster SuperFin version that powers the new Tiger Lake PC processors. Thus, we expect no performance-per-watt improvement relative to the 14nm++ Cascade Lake.

The Whitley 2S platform incorporates a pair of Ice Lake processors and a Lewisburg south bridge (PCH). Compared with Purley, Whitley adds two DRAM channels per socket for a total of eight, finally matching AMD’s Epyc. Like Cascade Lake, Ice Lake can handle a DDR4 module and an Optane module on each channel, and they now operate at up to DDR4-3200. Intel unveiled its second-generation Optane module (code-named Barlow Pass) as part of the recent Cooper Lake launch for scale-up (4S/8S) servers.

Intel highlighted Whitley’s PCIe Gen4 capability, a feature AMD shipped one year ago in its second-generation Epyc (Rome). It withheld Ice Lake’s PCIe lane count, but the die has four PCIe controllers. Assuming each controller has the same 16 lanes as those in Cascade Lake, the new processor should offer 64 lanes in total. The new 2S platform includes the Lewisburg-R south bridge (PCH), which launched with Cooper Lake. The south bridge is a holdover from Purley, except Intel disabled its integrated 10Gbps Ethernet ports. As an alternative to the integrated ports, we expect Whitley to launch with Intel’s Columbiaville (Ethernet Controller E810), which handles the newer 25/50/100Gbps Ethernet speeds as well as both the iWARP and RoCEv2 RDMA protocols.

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