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Imagination Series4 Tiles Tensors

November 17, 2020

Author: Mike Demler

Imagination Technologies’ new IMG Series4 deep-learning accelerators (DLAs) reduce DRAM bandwidth by splitting tensor operations into multilayer groups, enabling most intermediate data to remain on chip. At the recent Linley Fall Processor Conference, the company debuted the architecture, which can connect as many as eight cores to deliver a total of 100 trillion INT8 operations per second (TOPS).

Series4 is optimized for processing one item at a time (batch=1)—a requirement for most automotive systems. In an eight-core configuration, it runs ResNet-34 on large (1,200x1,200) images at 120fps with eight-millisecond latency. For a single-shot multibox detector (SSD) running ResNet-34 on 2,400x1,200 images, Imagination measured linear throughput scaling from one to eight cores. Along with convolutional neural networks (CNNs), Series4 can run long/short-term memory (LSTM) and other neural-network types. Imagination has already delivered to lead customers the Series4 IP, which is scheduled to begin general licensing in December.

Ceva and Synopsys provide similar multicore DLAs. Whereas Series4 requires a third-party host CPU, however, these competitors offer their inference engines with a DSP, bringing additional programmability for computer vision, new layer functions, and signal processing. Although the Series4 lacks some of the features available in other high-performance DLAs, its efficiency and low latency make it well suited for ADAS and autonomous vehicles.

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