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SimpleMachines Enables Flexible AI

January 5, 2021

Author: Bob Wheeler

Startup SimpleMachines has developed a new technology that approaches the flexibility of a GPU while promising the performance of a purpose-built deep-learning accelerator (DLA). To achieve this combination, it transforms neural-network graphs into four fundamental hardware behaviors, eliminating sequential-instruction semantics. At the lowest level, it uses reconfigurable hardware to create a data-flow architecture. At the top of the stack, it works with standard TensorFlow, fully abstracting the underlying hardware. SimpleMachines intends the architecture for a variety of neural-network models including Transformer, RNN, and MLP types in addition to common CNNs.

The company received first silicon of its 16nm Mozart inference chip in 4Q20 and is sampling a PCI Express card for high-volume servers. The chip has a tiled layout with 64 tiles in four rows. Designed to handle today’s large models as well as future models, it comes with in-package HBM2 memories that provide rapid access to 8GB of data. Mozart’s only high-speed external I/O is a PCIe Gen3 x16 host interface. SimpleMachines offers the chip on its Accelerando PCIe card, a half-height half-length 75W design, and expects to reach production in 3Q21.

Mozart employs a coarse-grain reconfigurable architecture (CGRA), a technique that has been a popular university-research topic since the early 1990s. As the name suggests, CGRA is similar to an FPGA in using reconfigurable connectivity, but instead of connecting individual gates, CGRA connects larger function blocks. This change eliminates much of the FPGA’s connectivity overhead, achieving near-ASIC performance on some algorithms while providing more flexibility than an ASIC. SimpleMachines is poised to deliver the first commercial CGRA product, not counting Wave Computing’s failed DPU design, which never reached production.

Subscribers can view the full article in the Microprocessor Report.

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