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EdgeCortix IP Lowers AI Latency

April 27, 2021

Author: Aakash Jani

EdgeCortix targets the high-end edge market with its custom intellectual property (IP), delivering class-leading ef­ficiency through a dual-accelerator approach. In simula­tion, the IP achieves top scores in among Level 3 ADAS accelera­tors for batch=1 performance on ResNet-50 and Yolo v3, with equally impressive power efficiency. The startup has yet to disclose any customers, but it is profit­able thanks to its IP and FPGA businesses.

To demonstrate this performance, the company is de­veloping a test chip that it estimates will execute 54 trillion operations per second (TOPS) in an 8W power en­ve­lope, as disclosed at the recent Linley Spring Processor Con­ference. The design reaches this peak throughput using an 800MHz clock and eight convolution engines. The chip will be manufac­tured in TSMC’s 12nm pro­cess; EdgeCortix expects first sil­icon early next year.

The startup is headquartered in Tokyo and has a design center in San Francisco. It has raised a mere $6 million through two funding rounds, one for US investors and the other for Asian investors. Although profitable, it’s now raising Series A funds to allow it to grow more quickly. EdgeCortix employs approximately 20 people led by CEO and founder Sakyasingha Dasgupta, who previously led an AI-optimization team at IBM Research.

EdgeCortix began as an IP licenser, com­bin­ing its DNA-branded deep-learning-accelerator (DLA) IP with Xilinx FPGAs for initial cus­tomers in the automobile, drone, and robot markets. Al­though the IP is highly con­figura­ble, the com­pany offers predesigned solu­tions. At the base of the prod­uct stack is the DNA-A050, which deliv­ers 1.8 TOPS from a single convolu­tion en­gine. Above it are the A100, A200, A400, and A800.

Subscribers can view the full article in the Microprocessor Report.

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