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Movellus Improves Clock Meshes

May 4, 2021

Author: Aakash Jani

Similar to how a person relies on a heartbeat, a chip relies on its clock to synchronize its complex operations, but an inefficient heartbeat impedes overall health. Startup Movellus uses its Maestro intellectual property (IP) to enhance clocking efficiency by up to 30%, boosting chip performance and saving power. The platform also accelerates timing closure by 5x, helping combat rising design costs.

An orchestra conductor is only as good as her performers, and the same holds for the Maestro platform. Movellus accompanies its platform with a collection of custom all-digital clocking IP, such as a smart-clock module (SCM), clock-generator module (CGM), and phase-shift module (PSM). The platform ties these elements together with custom methodology and software to create a “virtual mesh” topology that improves common clocking issues such as peak current rates, clock skews, and on-chip variation. Maestro is available now in production-quality IP. Customers such as Achronix, Mythic, and Syntiant have already adopted it into their silicon.

CEO Mo Faisal and CTO Jeff Fredenburg founded Movellus in 2014. Both earned doctorates from the University of Michigan and have a plethora of academic research experience. Faisal also served as a design engineer at Intel and PMC-Sierra. The Silicon Valley company has raised $21 million; its Series A round closed in 2019, led by Intel Capital and Candou Ventures. Movellus employs approximately 30 engineers.

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