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Intel Stacks Tiles on Ponte Vecchio

September 7, 2021

Author: Mike Demler

Intel calls Ponte Vecchio (PVC) its moonshot project because it hopes the launch will immediately close the sizable gap between its processors and the Nvidia GPUs that dominate the AI and high-performance-computing (HPC) segments. Rather than design one massive SoC like Nvidia’s Ampere A100, however, Intel employs its 2.5D and 3D interconnect technologies to build a heterogeneous design that integrates 47 active die, which it calls tiles, manufactured in five different process nodes.

On the basis of its first-pass (A0) silicon, Intel claims promising results. PVC integrates 128 Xe-HPC compute cores, which deliver 45 trillion FP32 flops per second from their vector engines and 1,468 INT8 TOPS from their matrix-processing units. Those performance numbers more than double the A100’s.

PVC’s initial ResNet-50 tests are less impressive, although we expect they’ll improve in production silicon. Inference runs just 13% faster compared with the A100, whereas training is about 20% faster. The company says PVC has run hundreds of GPU workloads, but ResNet-50 is the only one it has published. We’d prefer to see results on HPC workloads that better represent the processor’s target market.

Unfortunately, Intel withheld power-consumption measurements, which are critical for comparing PVC’s compute efficiency to that of other GPUs. It plans to ship the design in an OCP-compliant OAM module, however, limiting the high-power configuration to a maximum of 700W. If the tile-based accelerator is less power efficient than competitors—a distinct possibility—its raw-performance advantage will be meaningless. Nevertheless, the preliminary results are promising. If that performance holds for more-meaningful workloads, PVC may finally bridge Intel’s HPC gap.

Subscribers can view the full article in the Microprocessor Report.

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